1. Field of the Invention
The present invention relates to a Dynamic Random Access Memory (DRAM) device, and more particularly, to a DRAM cell, a DRAM and a method for fabricating the same.
2. Discussion of the Related Art
In general, a DRAM provides high memory capacity and low cost owing to its simple configuration, which includes a single transistor and a single capacitor. In this regard, it has been widely used in a variety of electrical products including computer systems. Recently, its application has been expanded.
Because of high memory capacity and increased processing speed trends in computers, a demand for DRAMs with high packing density exists in DRAM markets.
However, it is difficult to expect further increases in packing density in DRAMs having a single transistor and a single capacitor due to limitations imposed by the process technology, such as optical lithography using an infrared ray, generally adopted in fabricating such DRAMs.
A conventional DRAM cell will now be described with reference to the appended drawings. FIG. 1 shows a circuit diagram of a conventional DRAM cell. The conventional DRAM cell having a single transistor and a single capacitor includes a bitline, a wordline, an access transistor 2, a storage capacitor 4 and a sensing amplifier(not shown). A gate 6 of the access transistor 2 is connected to the wordline. The source 8 and drain 10 electrodes of the access transistor 2 are connected to the storage capacitor 4 and the bitline, respectively.
A plate electrode 12 of the capacitor 4 is connected to a reference voltage. An input port of the sensing amplifier is connected to the bitline and the other port is connected to the reference voltage. Data is stored in the storage capacitor 4 through the source and drain electrodes 8 and 10 from the bitline when the access transistor 2 is turned on. The stored data is transferred from the capacitor 4 to the bitline through the source and drain electrodes 8 and 10 when the access transistor 2 is turned on again. A logic value of the data stored in the capacitor 4 is determined by comparing a level of the transferred data with the reference voltage of the bitline.
The capacitor 4 of the DRAM cell generally includes a storage electrode 14 of n.sup.+ poly Si, a plate electrode 12 and a dielectric film between these two electrodes.
Data writing and reading operations in the DRAM cell having a configuration as aforementioned will now be described in detail. Electrons are redistributed on the surface of the storage electrode 14 under the dielectric film by means of a voltage equal to 1/2 Vcc applied to the plate electrode 12 when no data is stored in the storage electrode 14. Thus, a depletion layer of electrons is formed on the boundary of the dielectric film and the storage electrode 14.
The Vcc voltage is applied to the bitline and the wordline in writing data `1`. As a result, a gate electrode voltage and a source electrode voltage in the access transistor 2 increase to the Vcc voltage level so that the access transistor 2 is turned on.
A 1/2 Vcc-.DELTA.V voltage is applied to the storage electrode layer. The voltage difference .DELTA. is discussed in detail below. Therefore, electrons flow from the storage electrode layer having high potential to the source electrode 8 having low potential, thereby enlarging the depletion layer in the storage electrode layer. In addition, the depletion layer remains in the storage electrode layer if the wordline voltage is lowered to a ground potential voltage. This state of the cell indicates logic `1` in binary.
In writing data `0` in a memory cell, the Vcc voltage is applied to the gate 6 of the access transistor 2 under the state that the ground potential voltage is applied to the bitline. The electrons flow from the source electrode 8 having high potential to the storage electrode layer having low potential since 1/2 Vcc-.DELTA. voltage in the storage electrode layer is higher than the source electrode voltage `0`. As a result, the electrons are accumulated in the storage electrode layer and the depletion layer is restored to an accumulation layer.
The electrons remain in the storage electrode layer if the wordline voltage is lowered to the ground voltage. This state of the cell indicates logic `0` in binary. The data reading operation of the DRAM cell will be described below. The Vcc voltage is applied to the wordline while the bitline is pre-charged to a 1/2 Vcc voltage level. At this time, the access transistor 2 is turned on and the data stored in the storage electrode layer of the capacitor is transferred to the bitline. The voltage of the bitline varies depending on the stored charge quantity. The varied voltage of the bitline is compared with a reference voltage of a bitline in a dummy cell through the sensing amplifier which function as a comparator circuit. The voltage difference is amplified so that the logic value is determined as `1` when the varied voltage of the bitline is higher than the reference voltage. The logic value is determined as `0` when the varied voltage is lower than the reference voltage.
The voltage difference can be expressed as follows. EQU .DELTA.V=(1/2)Vcc Cs/(Cs+Cb)
Here, Cs is a storage capacitance and Cb is a bitline capacitance. The error caused by determining the logic value is reduced since the higher the Cs/Cb ratio is the higher the .DELTA.V voltage is. However, the conventional DRAM cell has several problems. The voltage difference .DELTA.V between the bitline voltage and the reference voltage based on which the sensing amplifier is capable of making a determination is about 100-200 mV or more. Thus, the storage capacitance to the bitline capacitance ratio .gamma. (where .gamma.=Cs/Cb) had better be high. The area of the cell is considerably reduced if the density of the DRAM increases, nevertheless, the bitline capacitance and the sensitivity of the sensing amplifier are not improved. For this reason, it is likely that the signal-to-noise ratio degrades and the cell transistor may malfunction.
The reliability of the DRAM cell may be degraded by a soft error due to .alpha. particles. That is, a pair of electron-holes occur by ionization impact when a .alpha. particle comes into collision with the semiconductor substrate. The minority carrier of the electron-holes is captured in the storage electrode varying the charge quantity therein. To eliminate such a soft error due to .alpha. particles, the area of the storage electrode has to be increased three-dimensionally or a dielectric layer having a high dielectric ratio has to be formed. However, the three-dimensional increase of the storage electrode causes higher steps therein, which makes forming the device through exposure and etching processes more difficult.
When forming the dielectric layer, it is difficult to obtain a high packing density of the DRAM cell due to undesired characteristics such as leakage current and breakdown voltage resulting from deficiencies in thin film fabrication techniques.